1/3 data briefing january 1999 complete data available on data-on-disc cd-rom or at www.st.com m28010 1 mbit (128k x 8) parallel eeprom with software data protection n fast access time: 100 ns n single supply voltage: C 4.5 v to 5.5 v for m28010 C 2.7 v to 3.6 v for m28010-w C 1.8 v to 2.4 v for m28010-r n low power consumption n fast byte and page write (up to 128 bytes) n enhanced write detection and monitoring: C data polling C toggle bit C page load timer status n jedec approved bytewide pin-out n software data protection n hardware data protection n software chip erase n 100000 erase/write cycles (minimum) n data retention (minimum): 10 years description the m28010 devices consist of 128kx8 bits of low power, parallel eeprom, fabricated with stmicroelectronics proprietary double polysilicon cmos technology. the devices offer fast access time, with low power dissipation, and require a sin- gle voltage supply (5v, 3v or 2v, depending on the option chosen). figure 1. logic diagram ai02221 17 a0-a16 w dq0-dq7 v cc m28010 g e v ss 8 table 1. signal names a0-a16 address input dq0-dq7 data input / output w write enable e chip enable g output enable v cc supply voltage v ss ground pdip32 (ba) plcc32 (ka) tsop32 (na) 8 x 20 mm 32 1
m28010 2/3 figure 2a. dip connections note: 1. du = do not use figure 2b. plcc connections note: 1. du = do not use a1 a0 dq0 a7 a4 a3 a2 a6 a5 a13 a10 a8 a9 dq7 a14 a11 g e dq5 dq1 dq2 dq3 v ss dq4 dq6 a12 du v cc ai02222 m28010 8 1 15 16 4 5 6 7 9 10 11 12 13 14 32 31 30 27 26 25 24 23 22 21 20 19 18 17 a15 du w a16 2 3 29 28 ai02223 du a8 a10 dq4 17 a0 a7 dq0 dq1 dq2 dq6 dq3 a6 a3 a2 a1 a5 a4 9 w a9 1 a16 a11 a14 a12 dq7 32 du v cc m28010 a15 a13 dq5 g e 25 v ss figure 2c. tsop connections note: 1. du = do not use a2 a1 a0 a6 a3 a5 a4 a9 a11 dq7 a8 g e dq5 dq0 dq1 dq3 dq4 dq6 a13 w a15 a7 a14 v cc a12 ai02224 m28010 8 1 9 16 17 24 25 32 v ss a10 dq2 du a16 du the device has been designed to offer a flexible microcontroller interface, featuring both hardware and software hand-shaking, with data polling and toggle bit. the device supports a 128 byte page write operation. software data protection (sdp) is also supported, using the standard jedec algo- rithm. the m28010 is designed for applications requiring as much as 100,000 write cycles and ten years of data retention. the organization of the data in a 4 byte (32-bit) word format leads to significant sav- ings in power consumption. once a byte has been read, subsequent byte read cycles from the same word (with addresses differing only in the two least significant bits) are fetched from the previ- ously loaded read buffer, not from the memory ar- ray. as a result, the power consumption for these subsequent read cycles is much lower than the power consumption for the first cycle. by careful design of the memory access patterns, a 50% re- duction in the power consumption is possible. ordering information devices are shipped from the factory with the memory content set at all 1s (ffh). the notation used for the device number is as shown in table 2. for a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the st sales office nearest to you.
3/3 m28010 table 2. ordering information scheme note: 1. this temperature range on request only. example: m28010 -10 w ka 6 t option t tape & reel packing speed -10 100 ns temperature range -12 120 ns 1 1 0 to 70 c -15 150 ns 6 C40 to 85 c -20 200 ns -25 250 ns operating voltage package blank 4.5 v to 5.5 v ba pdip32 w 2.7 v to 3.6 v ka plcc32 r 1.8 v to 2.4 v na tsop32: 8 x 20mm
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